Modern day electronic memory includes millions of memory cells, each respectively configured to store one or more bits of data (e.g., as an electric charge). Retrieval of data from a memory cell can be accomplished by a read operation, wherein electric charge stored in a memory cell is provided directly to a bit-line or sensed indirectly via the current of a transistor controlled by the charge. To conserve power, in one implementation, the electric charge generates a small voltage on the bit-line, which is subsequently amplified by a sense amplifier line into a “1” or a “0”, by amplifying the small change in the bit-line voltage into a full logic voltage swing (e.g., 2.5V) (e.g., in DRAM applications).
Various memory technologies typically have their read and write cycles synchronized with the processor clock. A memory controller dictates the timing of word and bit-lines. Based on the address, one row (i.e., word-line) through the word-line decoder is selected (e.g., by applying an appropriate voltage), while all the other non-selected word-lines remain at 0V. Each cell of the selected word-line is either directly tied to a (primary) sense amplifier or is chosen by a 1:N mux to a sense amplifier. A sense amplifier is a circuit that is able to recognize if a charge has been stored in the memory cell, and to translate this charge or lack of charge into a 1 or 0, respectively.
There may be as many sense amplifiers as there are memory cells on a word-line of a memory array. Each sense amplifier is connected to a column (i.e., bit-line). In some implementations several bit-lines share the same sense amplifier via muxes. After a predetermined time, all the cells of the entire word-line are read by the sense amplifier. This step may take a long time because the word-line has a high time constant due to the many memory cells that may be connected thereto. Subsequently, voltage sense amplifiers typically compare the voltage on a bit-line to a reference bias voltage and amplify this voltage difference to a full supply level (e.g., a VDD voltage). Other types of sense amplifiers (like current sense amplifiers) compare the effective current of a memory cell with a reference current from a current source. For example for non-volatile memories based on floating gate memory cells, the charge stored in the floating gate determines the threshold voltage of the memory cell transistor and the current flowing through the memory cell.
The time to activate a word-line and subsequently the sense amplifier ON and OFF (and the time duration in each state) may be based on predetermined timing sequences. These timing sequences are typically based on worst case condition assumptions to provide sufficient margin. For example, instead of basing the read timing on a nominal read access time when operating at 25° C., one or more guard-bands may be introduced with respect to one or more of the following variations: temperature, power supply, transistor parameter, aging, etc.
The control of the memory timing operation based on worst case scenarios contributes to additional power consumption and leads to reliability concerns. For example, keeping circuits ON for longer than necessary consumes additional power and may degrade the reliability of the components by exposing these circuits to higher voltages and/or currents for unnecessarily long durations to accommodate worst case margins. Also some sensing systems are controlled by clocked systems, where the clock cycle times of lower end products may be longer than the actual sensing times of the memories. For such lower end products the sense amplifiers and supporting circuits may be switched ON longer than necessary and thus consume more power.